Conventionally, a configuration is generally used in which correct signal amplification is carried out by using a closed amplifier for a circuit which contains an amplification stage thereinside, such as a pipeline ADC (Analog-Digital Converter).
However, although the closed amplifier can realize amplification in a high precision, it causes the increase of the consumed power in a high-speed operation. As a result, it is tended to increase the the consumed power of the ADC. Therefore, the approach is proposed in which the consumed power is suppressed by employing an open loop amplifier, a dynamic amplifier such as a comparator, and a passive amplifier by a passive device.
However, while these schemes can realize the high-speed operation and the low consumed power operation, it is difficult to realize linearity and a gain in a high precision independently. Thus, a usage method in which a calibration technique is combined is adopted.
Not only an inter-stage amplifier of the pipeline ADC but also an ADC which carries out a sampling operation are effective for these schemes in which signal amplification is carried out without the closed amplifier. If an amplification stage is provided after the sampling stage, an input conversion noise after sampling stage can be reduced and the noise request can be eased.
A technique which relates to the above technique is reported in Non-Patent Literature 1 and Patent Literature 1. In Non-Patent Literature 1, a method of simply realizing signal amplification by using a capacitance is described. In Patent Literature 1, a method of carrying out the amplification of only a differential signal by using a common mode reference voltage is proposed.
Also, a next generation mobile phone terminal requires that it is possible to handle various methods of LTE (Long Term Evolution) and LTE Advanced in addition to a conventional GSM (Global System for Mobile communication) method and the WCDMA (Wideband Code Division Multiple Access) method. For a signal received in each of these methods of one analog-digital convertor, the conversion rate as high-speed as about 40 MS/s (mega sample per second) and the high effective resolution of 11 bits or more are required.
Also, in the mobile terminal, a very small consumed power of the analog-digital convertor is required. Due to the miniaturization of the semiconductor manufacture process, an error factor of an analog circuit of the analog-digital convertor is corrected with a digital circuit, to improve the effective resolution. As the analog-digital convertor with low consumed power, an analog-digital convertor of a successive approximation type is suitable to carry out a digital correction. Moreover, as the analog-digital convertor of the successive approximation type which carries out a high-speed operation, the analog-digital convertor with a charge share-type successive approximation type according to the following Non-Patent Literature 2 more than the analog-digital convertor of a charge share type successive approximation type's being suits.
In the microcomputer of the next generation, as the multi-function develops, the analog-digital convertor of the high speed and high resolution is required. As the analog-digital convertor mounted on a microcomputer, the effective resolution of 11 bits or more is often required.
Also, in case of the microcomputer, especially, it is required that chip size of the analog-digital convertor is small. Therefore, the analog-digital convertor of the successive approximation type which carries out the digital correction is more suitable than the analog-digital convertor of a pipeline type which carries out the digital correction. Moreover, because the high-speed operation of tens of MS/s or higher is required in many cases, the analog-digital convertor of a charge share-type successive approximation type is suitable.
The analog-digital convertor of the charge share-type and successive approximation type which carries out a digital correction has one feature that a high resolution can be realized in the small chip size and consumed power in the conversion rate of about 100 MS/s or below. Therefore, the wide application such as SoC (System on a Chip) technique is thought of in addition to the above convertor.
A comparator for the analog-digital convertor is disclosed in Patent Literatures 2 and 3.
Non-Patent Literature 3 discloses an approach which improves an effective resolution, by setting an input full scale range to Rail-to-Rail, in the analog-digital convertor of the charge redistribution-type and the successive approximation type which carries out the digital correction. That is, by using from the power supply voltage VDD to the grounding voltage completely, a signal component is maximized in SNR (Signal to Noise Ratio).
Also, many conventional analog-digital convertor of the successive approximation type disclose the approaches which improve an effective resolution by fundamentally reducing a quantity of noise generated by a comparator known as a dominant noise source of the analog-digital convertor. The noise voltage level of the comparator is inversely proportion to a square root of the capacitance. Therefore, by increasing a capacitance value to 4 times, the noise can be reduced to a half. When the capacitance is increased to 4 times, it needs to maintain a conversion rate by increasing the consumed power of the comparator to 4 times to maintain a response speed.
Non-Patent Literature 4 discloses an analog-digital convertor of a charge redistribution-type and a successive approximation type which carries out the determination of each of bits in a first half from the MSB (Most Significant Bit). Next, a conversion residual after the conversion of the first half is amplified by an intermediate amplifier and the analog-digital conversion is carried out to the amplified residual. Thus, each of bits of the second half to the LSB (Least Significant Bit) is determined. In this way, because the noise level which is required for the comparator can be eased for the gain of the above-mentioned intermediate amplifier, the influence by the noise of the comparator can be substantively made small.
Non-Patent Literature 5 discloses a sigma-delta analog-digital convertor which is known to be possible to output a high resolution.